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Lowest Power 10G SERDES !
August 2004
XPIO 110GXS
Fully Integrated 10Gbps Serializer/Deserializer Device
Data Sheet
Features

General Description
The XPIOTM 110GXS is a fully integrated 10 Gbps serializer/deserializer device designed for high-speed switches and routers that require very low power budget and a small footprint as well. Centering on 10 Gbps speed, the XPIO 110GXS is a versatile chip that is capable of handling applications in various standards, such as OC-192 (9.95 Gbps) and 10GE (10.31 Gbps). An on-chip low jitter PLL generates all required clocks based on an external reference clock at 1/16 or 1/64 frequency of the serial data rate, which is 622.08 MHz or 155.52 MHz, respectively, for OC-192 applications. An Integrated Limiting Amplifier allows flexibility in placement and reduced bit-error rates (BER). Fabricated with state-of-the-art CMOS technology, the XPIO 110GXS performs all necessary functions for serial-to-parallel and parallel-to-serial conversions, and consumes less than one third of the power consumed by the more conventional SiGe Bi-CMOS designs.
Single chip SERDES solution with integrated transmitter and receiver Continuous serial operation range from 9.95 Gbps to 10.31 Gbps Parallel LVDS data range from 622 Mbps to 644 Mbps Low power consumption (800 mW typical) Performs 16:1 serialization and 1:16 deserialization Embedded Limiting Amplifier enhances receiver sensitivity Low-jitter PLL for clock generation On-chip Clock Data Recovery circuit On-chip FIFO to decouple transmit clocks Bit order swap for 10GE operations Programmable 4-phase LVDS clock output for easy system design Repeating serial data output Line loopback, diagnostic loopback, and simultaneous loopback modes Frequency Lock Alarm Output Programmable differential output swing on both Serial driver and Parallel LVDS driver 1.3V core voltage and 2.5V I/O voltage Supports 10GE (10-Gigabit Ethernet), OC-192, XFP, XSBI and SFI-4.1 interfaces 269-pin flip-chip BGA (15 x 15 mm body size, 0.8 mm pitch) -40 to 85C operating temperature
Overview
The XPIO 110GXS consists primarily of blocks of parallel-to-serial and serial-to-parallel functions plus system timing. Low Voltage Differential Signaling (LVDS) is used for parallel signal input and output while Current Mode Logic (CML) is used for serial transmission and reception. A limiting amplifier is designed into the chip to improve serial receiver sensitivity. The system timing blocks consist of the clock-multiplier-unit (CMU), LVPLL (LVDS interface timing Phase-Lock-Loop) and CDR (clock-data-recovery) units, which generate clocks for the chip. Figure 1 shows the XPIO 110GXS chip block diagram.
Table 1. XPIO 110GXS Supported Protocols
Device XPIO 110GXS Standards Supported OC-192 10GE Data Rate 9.95 Gbps 10.31 Gbps
(c) 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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Lattice Semiconductor
Figure 1. XPIO 110GXS Block Diagram
XPIO 110GXS Data Sheet
RX_LOS_POL LB_LVDS_Enb RX_LV_EN RX_CLK RX_D_LV_P[0] RX_D_LV_N[0] . . . RX_D_LV_P[15] RX_D_LV_N[15] RX_CK_LV_P * RX_CK_LV_N RX_LV_CKDLY[1:0] SC_LV_ISET[1:0] Deserializer 1:16 DEMUX Clock Data Recovery 1 0 0 LVDS Output 0 1 Bit Order Logic 1 16 RX_LOS RX_REF_CK_Enb RX_REF_CK_P RX_REF_CK_N REF_CK_P REF_CK_N RX_D_RP_Enb RX_D_RP_P RX_D_RP_N SC_LOCK_DIFF[1:0] RX_FILT_EXT_P RX_FILT_EXT_N RX_LOCK RX_LOCK2REFb
Serial Data
SC_LSB1STb
Limiting Amplifier
RX_D_P RX_D_N
REF_CK_SEL CK622OUT_P CK622OUT_N LB_P622_Enb TX_D_LV_P[0] TX_D_LV_N[0] . . . TX_D_LV_P[15] TX_D_LV_N[15] 1 0 Bit Order Logic 16 1 0 CMU 622 Out TX_CP_ISET[1:0] Clock Multiplier Unit
TX_CK622_PA[1:0] TX_LOCK TX_FILT_EXT_P TX_FILT_EXT_N CK622OUT_SEL
LVDS Input
TX_CLK
FIFO_WRITE_CK TX FIFO
Serializer 16:1 MUX
TX_LV_PLLBPb
0
1
FIFO_RD_CK TX_FIFO_INIT TX_FIFO_ERR
TX_CK_LV_P TX_CK_LV_N TX_CK_LV_PA[1:0] TX_CK_LV_SEL
LVPLL
TX CML DRIVER
TX_D_P TX_D_N TX_D_EN TX_CML_ISET[1:0]
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Lattice Semiconductor
XPIO 110GXS Data Sheet
The XPIO 110GXS is divided into a transmitter section and a receiver section. The major operations performed by the chip are: Transmitter Operation 1. Low jitter clock generation via the Clock-Multiplier-Unit (CMU) 2. 16-bit LVDS parallel data input 3. Parallel-to-serial conversion 10Gbps CML serial data output Receiver Operation 1. CML serial input to a limiting amplifier 2. Clock and data recovery 3. Serial-to-parallel conversion 4. 16-bit LVDS parallel data output, with a synchronizing clock output 5. Built-in LVDS line loopback, and LVDS diagnostic loopback modes for testing and network diagnosis
Functional Description
The XPIO 110GXS transceiver is a low power, low jitter, and fully integrated serializer/deserializer chip. It operates in the data rate range of 9.95-10.31 Gbps, performs all necessary parallel-to-serial and serial-to-parallel conversions. The chip is suitable for applications utilizing OC-192 and 10GE. The serial interface I/O uses the CML standard while the low speed parallel I/O is based on the LVDS standard. These standards are compliant to both the Optical Interface Forum's SFI-4 standard and the 10GE's XSBI standard. The LVDS parallel I/O can be directly connected to Multi-Standard-Agreement (MSA) 300 systems. To accommodate bit order differences between OC-192 and 10GE, the XPIO 110GXS provides the capability of bit swapping. The data presented on TX_D_LV_P/N[15] or MSB is transmitted first, followed in order by TX_D_LV_P/N[14] to TX_D_LV_P/N[0] when SC_LSB1STb is not connected or is connected to a logic high. TX_D_LV_P/N[0] or LSB is transmitted first followed in order by TX_D_LV_P/N[1] to TX_D_LV_P/N[15] when SC_LSB1STb is connected to a logic low. The parallel receive bus mirrors this behavior. The SC_LSB1STb unconnected, or at logic high, the first serial bit received is presented on RX_D_LV_P/N[15]. Conversely the first bit received is presented on RX_D_LV_P/N[0] when SC_LSB1STb is pulled low.
Transmitter
The transmitter performs the serialization process, converting the 16-bit parallel LVDS data stream to a serial data stream at approximately a 10 Gbps data rate. The transmitter consists of a LVDS data receiver, a FIFO, a 16:1 serializer, a low jitter CMU, and a 10Gbps output data driver. LVDS Data Receiver The Input and Analog Pin Assignments and Descriptions table in this document shows the 16 LVDS differential data input pairs (TX_D_LV_P/N [15:0]). Data applied at the transmit data pairs is aligned to the LVDS input clock (TX_CK_LV_P/N), which can be either 1/16th or 1/32nd the transmit data rate (622.08 or 311.04 nominally for OC192). The clock rate is selected through the assertion or deassertion of the TX_CK_LV_SEL pin. Figure 13 describes the LVDS data relationship to the LVDS input clock. The LVDS input receivers convert the LVDS signals to CMOS signals. The converted signals are latched based on an internal clock that is generated from the TX_CK_LV_P/N input clock through a phase-lock-loop (LVPLL). In order to achieve optimal latch timing, the phase relationship between the internal clock and the TX_CK_LV_P/N clock can be adjusted by programming TX_CK_LV_PA[1:0]. The LVDS PLL can also be bypassed by the assertion of the TX_LV_PLLBPb pin, which is a desirable feature in some applications. When the LVPLL is bypassed it is up to the system designer to manage the TX_CK_LV_P/N input. Transmitter FIFO A 16 bit wide and 8-word deep FIFO is designed into the XPIO 110GXS to decouple the LVDS clock from the serial transmission clock. In addition, the FIFO also improves the tolerance to minor phase differences between the FIFO write clock and read clock due to phase drift or phase wander.
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Lattice Semiconductor
XPIO 110GXS Data Sheet
The FIFO circuitry indicates an overflow or underflow condition by asserting TX_FIFO_ERR high. The TX_FIFO_ERR only provides status information about an overflow or underflow. It does not indicate which of the two events actually occurred. During the period of time when the TX_FIFO_ERR signal is asserted, the TX_D_P/N pins toggle at a constant rate. This prevents the AC coupling capacitors from becoming blocking capacitors. The transmit FIFO's read and write pointers can be recentered by asserting the TX_FIFO_INIT pin high. Thus, one way to automatically recenter the FIFO read/write pointers after TX_FIFO_ERR is asserted is to connect TX_FIFO_INIT and TX_FIFO_ERR together. The FIFO read/write pointers are re-centered after: * Device power on reset * Transmitter reset (asserting RESET_TXb low) * CMU PLL is out of lock Serialization The output data bus from the FIFO feeds a 16:1 serializer to generate a 9.953 Gbps (OC-192 rate) data stream. The high-speed clock (TX_CLK) is a low jitter clock generated by the CMU. The serializer uses TX_CLK to clock out high-speed data. TX CML Driver The serial data stream in turn becomes an input to a differential high-speed CML data driver. The TX_D CML driver incorporates an internal 50-ohm termination resistor on both P and N branches for impedance matching with the PCB transmission line. The CML output may require AC coupling (as in Figure 5). The output current of the CML driver can be adjusted using two configuration pins, TX_CML_ISET[1:0]. These configuration pins are used to balance power consumption and performance. In normal operation, the data presented at the LVDS TX inputs requires about nine clocks to transit the various logic blocks before being presented at the TX CML driver output. Clock-Multiplier-Unit (CMU) The CMU consists of a differential PLL that is capable of producing a very low jitter serial clock. The clock is generated through a reference clock (REF_CLK_P/N) at either 1/16th or 1/64th the data transmission rate (This is nominally 622.08 or 155.52 MHz for OC-192 data rates). This reference clock must be generated from a differential crystal oscillator that has a frequency accuracy of better than 20ppm for SONET applications. The CMU PLL can provide a phase-adjustable parallel data rate clock (CK622OUT_P/N) that is 1/16th the transmit data rate to clock other devices or systems. The output of CK622OUT_P/N meets the LVDS signaling specifications. Using the TX_CK622_PA[1:0] configuration pins, the phase can be adjusted in T/4 increments, where T is the period of the clock for the parallel interface.
Receiver
Limiting Amplifier The XPIO 110GXS 10 Gbps CMOS receiver integrates a highly sensitive limiting amplifier. The XPIO 110GXS also implements an amplifier offset compensation technology that works in conjunction with the limiting amplifier to achieve superior amplifier input sensitivity. Sufficient gain is designed into the limiting amplifier to detect a peak-topeak differential input as small as 50mV. This attenuated signal can be properly detected and amplified to saturation. Clock and Data Recovery (CDR) One of the most critical circuits in the receiver is the clock and data recovery (CDR) block. The CDR block extracts the clock from an incoming high-speed, non-return to zero (NRZ) data, and retimes the data based on an external reference clock. Extraction of the clock embedded in the serial data-stream is performed through comparison of the phase relationship between transitions of the data and the external reference clock.
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XPIO 110GXS Data Sheet
The external reference clock is essential for the CDR block. The reference clock provides two functions: One function is training the VCO in the CDR PLL to the serial data-stream frequency. The other is to generate a stable clock when the input serial data is absent. The CDR PLL creates an internal reference frequency. The reference frequency is monitored, and a loss of lock is asserted when it goes out of specification. Lock Detect The XPIO 110GXS implements a CDR lock detector circuit that monitors the frequency of the internal clock. RX_LOCK is asserted whenever a REF_CK or RX_REF_CK are operating within specification. RX_LOCK is deasserted under some specific circumstances: 1. When RX_RESETb is asserted (i.e. `0') 2. When the REF_CK (or RX_REF_CK) is not present. 3. When the clock recovered from the incoming datastream falls outside the range specified by the SC_LOCK_DIFF input pins. When the recovered clock is out of range, RX_LOCK will deassert briefly and then be reasserted as it relocks to the REF_CK (RX_REF_CK). This effectively leaves the RX_LOCK signal toggling as it attempts to reacquire the clock embedded in the RX_D_P/N data inputs. Deserialization The XPIO 110GXS uses a 1:16 demultiplexer to deserialize the high speed data from the CDR. The demultiplexer generates the 16 bit parallel data stream. The bit order presented on the RX_D_LV_P/N[0..15] LVDS outputs mirrors the order on the TX_D_LV[0..15]P/N LVDS inputs. The first data bit received by the CDR is present on RX_D_LV_P/N[15] when SC_LSB1STb is connected to a logic high, and it is present on RX_D_LV_P/N[0] when SC_LSB1STb is connected to a logic low. LVDS Data Transmitter The 16-bit parallel data and clock are sent out via the RX_D_LV_P/N[0..15] and RX_LV_CK_P/N LVDS pins, respectively. Data on the RX_D_LV_P/N pins is synchronous to the RX_LV_CK_P/N output pins. The data coming in on the RX_D_P/N pins requires around five clocks to arrive at the RX_D_LV_P/N outputs. The output current of the LVDS outputs is adjustable using the SC_LV_ISET[1:0] configuration pins. System designers can use these pins to optimize the LVDS receive data performance. XFP Module Considerations The XPIO110GXS was conceived and implemented prior to the finalization of the XFP specification. The implication of this is the CML TX voltage swing is typically higher than that specified in the XFP MSA documents. The XFP MSA specification indicates a XFP module should accept a maximum of 800mV input swing. In practice it is the individual XFP module internal architecture that defines the maximum range. However, most XFP modules simply rate themselves to the 800mV specification regardless of the likelihood they may operate beyond the range specified in the XFP MSA. Actual operation of the XPIO110GXS with existing XFP modules shows these still operate with the CML swing set to the default TX_CML_ISET[1:0] = "11". In order to more closely match the XFP specification a TX_CML_ISET[1:0] = "01" configuration is recommended. This places the typical output swing from the CML TX outputs at 650mV to 1100mV.
Loopback Operation
The XPIO 110GXS supports several loopback operations to provide diagnostic functions and to aid in performing SONET/SDH functional tests. LVDS Diagnostic Loopback In LVDS loopback mode, 16 bit-wide data is fed into the TX LVDS input. The XPIO 110GXS routes data from the LVDS transmit interface to the internal receiver interface, and then repeats the data at the LVDS RX output. To enable this mode of operation set BIST_ENb=0, LB_LVDS_ENb=0, and BIST_LB_SC[1:0]=10.
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Figure 2. LVDS Loopback Mode Block Diagram
LB_LVDS_ENb=0 BIST_ENb=0 BIST_LB_SC0=0 BIST_LB_SC1=1 RX_D_LV[0..15] RX_CK_LV_P/N RX LVDS Data 1 0 Deserializer
XPIO 110GXS Data Sheet
RX_D_P 10G RX RX_D_N
LVDS Clock Bypass
LVDS Data Loopback
TX_D_P TX_D_LV[0..15] TX_CL_LV_P/N TX LVDS Data 1 0 Serializer 10G TX TX_D_N
CMU REF_CK_P/N
LVDS Line Loopback
Line loopback is a diagnostic mode that establishes a parallel connection between the output of the deserializer and the input to the serializer. When this mode is active, serial receive data is deserialized, and internally looped back to the serializer. The data provided at the serializer is transmitted via the CML output. Line loopback is activated by setting the LB_P622_Enb pin to a logic low. Mode 1: Synchronous line loopback without clock clean-up. Driving LB_P622_Enb low enables line loopback mode. Connecting the LVDS output clock, RX_CK_LV_P/N, to REF_CK_P/N makes the loopback mode synchronous. In addition, a separate reference clock is input to RX_REF_CKP/N for use by the CDR logic. The data transmitted across the TX_D_P/N pins is now timed to the LVDS clock making the RX and TX data synchronous. However, the RX_CK_LV_P/N does not require SONET/SDH tolerance in order to transmit the parallel LVDS data. This means the data repeated on TX_D_P/N will have significant jitter. Figure 3. Line Loopback Mode 1 Block Diagram
LVDS Loopback Mode 1 LB_LVDS_ENb=1 BIST_ENb=0 BIST_LB_SC0=0 BIST_LB_SC1=1 RX_D_LV[0..15] RX_CK_LV_P/N RX LVDS Data 1 0
Deserializer
RX_D_P 10G RX RX_D_N
LB_P622_ENb=0
Parallel Loopback
TX_D_P TX_D_LV[0..15] TX_CL_LV_P/N TX LVDS Data 1 0 Serializer 10G TX TX_D_N
CMU REF_CK_P/N
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XPIO 110GXS Data Sheet
Mode 2: Synchronous line loopback with clock clean-up. Driving LB_P622_Enb low enables line loopback mode. In order to make this loopback mode SONET/SDH compliant the CK622OUT_P/N must be connected to a VCXO-powered PLL chip (e.g. MAX3670), and CK622OUT_SEL pulled/driven high. The output of the PLL provides a low jitter reference clock that is in phase with the data presented at the LVDS parallel outputs. This reference clock is connected to REF_CK_P/N. As in Mode 1 a separate reference clock is input to RX_REF_CK_P/N to drive the CDR logic. Data on the TX_D_P/N and RX_D_P/N pins are now synchronous, and the data repeated on TX_D_P/N meets SONET/SDH line loopback application requirements. Figure 4. Line Loopback Mode 2 Block Diagram
LVDS Loopback Mode 1 LB_LVDS_ENb=1 BIST_ENb=0 BIST_LB_SC0=0 BIST_LB_SC1=1 RX_D_LV[0..15] RX_CK_LV_P/N RX LVDS Data 1 0 Deserializer 10G RX RX_D_N
RX_D_P
LB_P622_ENb=0
Parallel Loopback
TX_D_P
1
TX_D_LV[0..15] TX_CL_LV_P/N
TX LVDS Data
0
Serializer
10G TX TX_D_N
CMU REF_CK_P/N Low Jitter Clock Synchronous to REF_CK_P/N CK622_OUT_PN CK622OUT_SEL = 1 External Low Jitter PLL (e.g. MAX 3670) To REF_CK_P/N
Reference PLL
Reference Clocks
There are two AC coupled reference clock input pairs, REF_CK_P/N, and RX_REF_CK_P/N. The CDR block is driven by either REF_CK_P/N or RX_REF_CK_P/N. The CMU block is only driven by REF_CK_P/N. The reference clock input frequency for REF_CK_P/N can be either 1/16th (622MHz) or 1/64th (155MHz) the transmitter/receiver data rate. Likewise, RX_REF_CK_P/N can be 1/16th or 1/64th the 10Gbps receiver rate. RX_REF_CK_P/N and REF_CK_P/N are configured in tandem to 1/16th or 1/64th by REF_CK_SEL. They cannot be configured independently. AC coupling for all reference clocks is recommended.
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Driving RX_REF_CK_P/N is only necessary when: * The transmitter and receiver run at independent data rates * Line Loopback Mode 1 is active * Line Loopback Mode 2 is active
XPIO 110GXS Data Sheet
Figure 5 shows how a reference clock is input to the XPIO 110GXS using an AC coupling scheme. Figure 5. CML Output Driver Termination (AC Coupled)
VDD 50 0.1F
VDD 50
50
50
0.1F
Zo = 50
XPIO 110GXS
External
Figure 6. CML Input Receiver (AC Coupled)
DCFB
VDD
0.1
0.1
Z0 = 50 50 50
External
XPIO
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Lattice Semiconductor
XPIO 110GXS Data Sheet
Figure 7. Differential Oscillator Driving to XPIO 110GXS Clock Input (AC Coupled)
0.1F
0.1F
Zo = 50
100
External
XPIO 110GXS
Figure 8. LVDS Output and Input Connection
Zo = 50
100
LVDS Output
External
LVDS Input
Figure 9. External Loop Filter Components
0.01 F 0.39F
396
396
TX_FILT_EXTP
TX_FILT_EXTN
RX_FILT_EXTP
RX_FILT_EXTN
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Lattice Semiconductor PCB Layout Recommendations
XPIO 110GXS Data Sheet
The TX/RX filter components should be small form factor capacitors and resistors. They should be placed as close as possible to the XPIO 110 device. The TX filter components should be surrounded by a copper trace to GND. As shown below, the RX filter components should be enclosed by the GND. Figure 10. PCB Layout Examples
TX External Filter PCB Layout Example
13 14 15 16 17 A B C D E L M N
RX External Filter PCB Layout Example
1 2 3 4 5
GND Pin
GND Copper Trace GND Pin
GND Copper Trace
Bottom View These diagrams for example purposes only.
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Lattice Semiconductor
XPIO 110GXS Data Sheet
Electrical Specifications
AC Signaling Definitions
Figure 11. Differential Voltage Measurements
V
V+ VICM, VOCM V-
VIS, VOS
T
V+ -V-
VID, VOD =2 x VIS, VOS
T
Figure 12. Rise and Fall Time Measurements
80%
20%
tR
tF
Figure 13. LVDS Data to Clock Relationship of Transmitter, 1/16 th of Frequency (622.08MHz for OC-192)
TX_CK_LV_N, TX_CK_LV_SEL = 1, fclk = 622.08MHz tSU tHD tCKH tCKP
TX_D_LV_P/N[15:0]
Note: TX_D_LV_P/N[15:0] is latched using the rising edge of TX_CK_LV_N.
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XPIO 110GXS Data Sheet
Figure 14. LVDS Data to Clock Relationship of Transmitter, 1/32 nd of Frequency (311.04MHz for OC-192)
TX_CK_LV_P, TX_CK_LV_SEL = 0, fclk = 311.04MHz tSU tCKH tCKP
tHD TX_D_LV_P/N[15:0]
Figure 15. LVDS Data to Clock Relationship of Receiver
RX_D_LV_P/N[15:0]
tCQB RX_CK_LV_P tCQA
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Lattice Semiconductor Configuration Pin Descriptions
Pin Name Transmitter Controls TX_D_EN 1 0 1 TX_LV_PLLBPb 0 1 0 11 TX_CML_ISET[1:0] 10 01 00 11 TX_CK622_PA[1:0]1 10 01 00 RESET_TXb PWDN_TXb TX_CK_LV_SEL 1 0 1 0 1 0 11 10 01 TX_CK_LV_PA[1:0] 00
nd
XPIO 110GXS Data Sheet
State TX_D_P/N output is active TX_D_P/N output is inactive. The internal LVDS PLL is active
Action
The internal LVDS PLL is bypassed. External clock management and phase adjustment is required when this pin is 0. Initialize the TXFIFO No action See VOD in the High Speed Input/Output Specifications section of this data sheet. 3T/42 Adjust T/2 Adjust T/4 No Adjust Transmitter in normal operation Resets the transmitter Transmitter is operating Transmitter is powered down TX_CK_LV is 1/16 of frequency TX_CK_LV is 1/32 of frequency Clock delay = 0 Clock delay = -T/16 Clock delay = T/16 Clock delay = T/8 Clock delay = T/4 Clock delay = T/4-T/32 Clock delay = T/4+T/32 Clock delay = T/4+T/16 622MHz clock (default using internal pull-ups) Invalid Invalid 155MHz clock RX_REF_CK is disabled RX_REF_CK is enabled LVDS output clock is delayed: 90ps LVDS output clock is delayed: 180ps LVDS output clock is delayed: 270ps LVDS output clock is delayed: 360ps
TX_FIFO_INIT
TX_CK_LV_SEL = 1/16th of Frequency
TX_CK_LV_SEL = 1/32 of Frequency 11 10 01 00 11 10 01 00
TX_CP_ISET[1:0]
Receiver Controls RX_REF_CK_ENb 1 0 11 RX_LV_CKDLY[1:0] 10 01 00
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Lattice Semiconductor Configuration Pin Descriptions (Continued)
Pin Name State RX_LOS_POL = 0 1 RX_LOS 0 RX_LOS_POL RX_D_RP_ENb RX_LOCK2REFb3 1 0 1 0 1 0 11 SC_LOCK_DIFF[1:0]3 10 01 00 11 SC_LV_ISET[1:0] 10 01 00 RX_LV_EN PWDN_RXb RESET_RXb General Controls CK622OUT_SEL 1 0 1 SC_LSB1STb 0 REF_CK_SEL4 BIST_ENb 1 0 1 0 11 BIST_LB_SC[1:0] 10 01 00
1. 2. 3. 4.
XPIO 110GXS Data Sheet
Action RX_LOS_POL = 1 Asserted by the receiver to indiReceiver OK cate it has lost the data signal. Receiver OK RX_LOS is an active-low input RX_LOS is an active-high input. RX_D_RP_P/N signals are inactive RX_D_RP_P/N signals are active RX_PLL locks to the recovered receive data clock. RX_PLL locks to the REF_CK or RX_REF_CK input See LOCKTOL in the High Speed Input/Output Specifications section of this data sheet. Asserted by the receiver to indicate it has lost the data signal.
See VOS in the Low Speed Input/Output Specifications section of this data sheet. RX_D_LV_P/N[15:0] are enabled RX_D_LV_P/N[15:0] are disabled Receiver is operating Receiver is powered down Receiver normal operation Resets the receiver logic. CK622 sourced by CDR CK622 sourced by CMU TX_D_LV_P/N[15] transmitted over TX_D_P/N first RX_D_LV_P/N[15] first bit received from RX_D_P/N (e.g. SONET applications) TX_D_LV_P/N[0] transmitted over TX_D_P/N first RX_D_LV_P/N[0] first bit received from RX_D_P/N (e.g. 10GE applications) REF_CK is 1/16 of frequency (622.08MHz for OC-192) REF_CK is 1/64 of frequency (155.52MHz for OC-192) Normal operation, built-in self tests are disabled. Built-in self test enabled. Enable this for LVDS loopback mode only. Invalid LVDS loopback mode enable Invalid Invalid
1 0 1 0 1 0
Only available when CK622OUT_SEL = 0 (CMU CLK Mode). T = period Locks to REF_CK when RX_REF_CK_Enb = 1. Locks to RX_REF_CK when RX_REF_CK_Enb = 0. Applies to RX_REF_CK also.
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Lattice Semiconductor
XPIO 110GXS Data Sheet
Absolute Maximum Ratings1, 2, 3
1.3V Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 1.43V 2.5V Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.75V DC Input Voltage (Differential Inputs). . . . . . . . . . . . . . -0.3 to VDD25 + 0.3V DC Input Voltage (LVCMOS Inputs) . . . . . . . . . . . . . . . -0.3 to VDD25 + 0.3V Output Current (Differential Outputs) . . . . . . . . . . . . . . . . . . . 50 mA Output Current (LVCMOS Outputs) . . . . . . . . . . . . . . . . . . . . 15 mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150C Case Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . -55 to 125C
1. Stress above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied (while programming, following the programming specifications). 2. Thermal characteristics, maximum ratings, and thermal compliance requirements can be found in the Lattice Thermal Management document. 3. All voltages referenced to GND.
Recommended Operating Conditions
Parameter Ambient Temperature (Commercial) Ambient Temperature (Industrial) Symbol TA TA VDDAR VDDAT VDDL VDDT VDDR VDDAT25 VDDAR25 VDDH Test Condition Min. 0 -40 Typ. Max. 70 85 Units C C
1.3V Supply Voltage
1.23
1.30
1.37
V
2.5V Supply Voltage
2.37
2.5
2.63
V
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Lattice Semiconductor
XPIO 110GXS Data Sheet
Electrical Characteristics
High Speed Input/Output Specifications
Over Recommended Operating Conditions
Symbol AC Characteristics tR tF fREFCLK CML output rise time CML output fall time Input reference clock frequency (REF_CK_P/N) See Figure 12. See Figure 12. REF_CK_SEL = 1 REF_CK_SEL = 0 -- -- 622.08 155.52 622.08 155.52 40 -100 35 35 -- -- -- -- -- -- 45 45 644.53 161.13 644.53 161.13 60 100 ps ps MHz MHz MHz MHz % ppm Parameter Test Conditions Min. Typ. Max. Units
fREFCLK tDCREF
Receiver input reference clock REF_CK_SEL = 1 frequency (RX_REF_CK_P/N, active only in applications where REF_CK_P/N is used as REF_CK_SEL = 0 a transmitter) Reference clock duty cycle
fREFCLK Reference clock frequency tolerance DC Characteristics VCOM Serial output common mode voltage (TX_D_P/N) VDDT = 1.3V, See Figure 11. VDDT = 1.3V, TX_CML_ISET[1:0]=11, See Figure 11. VOD Serial output differential voltage swing (TX_D_P/N) VDDT = 1.3V, TX_CML_ISET[1:0]=10 VDDT = 1.3V, TX_CML_ISET[1:0]=01 VDDT = 1.3V, TX_CML_ISET[1:0]=00 VID VICM VID Serial input differential voltage swing (RX_D_P/N) Serial input common mode voltage (RX_D_P/N) Input voltage differential swing for (REF_CK_P/N, RX_REF_CK_P/N) Transmitter jitter generation (peak to peak) Transmitter CMU PLL acquisition time SC_LOCK_DIFF[1:0] = 11 LOCKTOL Frequency difference at which receiver PLL goes out of lock SC_LOCK_DIFF[1:0] = 10 SC_LOCK_DIFF[1:0] = 01 SC_LOCK_DIFF[1:0] = 00 JTOL tACQ Receiver jitter tolerance Receiver PLL acquisition time See Figure 11. See Figure 11. See Figure 11.
0.65 1100 1000 650 1250 50 0.75 250
-- -- -- -- -- -- -- --
1.0 1750 1500 1100 1800 2000 1.15 2400
V
mV (pk-pk)
mV (pk-pk) V mV (pk-pk) UI S ppm ppm ppm ppm
Performance Characteristics JGEN tACQ -- -- -- -- -- -- 0.085 10 1200 600 1200 600 -- -- -- -- -- --
Exceeds SONET Jitter Tolerance Mask -- 10 -- S
Note: Reference clock input characteristics should meet the following requirements for SONET/SDH applications: -125 dBc/HZ @ 1 MHz offset -105 dBc/HZ @ 100 KHz offset
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Lattice Semiconductor
XPIO 110GXS Data Sheet
Electrical Characteristics (Continued)
Low Speed Input/Output Specifications
Over Recommended Operating Conditions
Symbol AC Characteristics tR tF tCQB tCQA fCLKOUT tDCCLK tR tF LVDS output rise times LVDS output fall times LVDS output data invalid prior to LVDS output clock LVDS output data invalid after LVDS output clock LVDS output clock frequency, OC192 rate (CK622OUT_P/N, RX_CK_LV_P/N) LVDS output clock frequency duty cycle (CK622OUT_P/N, RX_CK_LV_P/N) LVDS input rise times LVDS input fall times tCKH/tCKP See Figure 13. See Figure 12. See Figure 12. See Figure 13. TX_CK_LV_SEL =1, TX_CK_LV_PA[1:0]=11 tSU See Figure 13. TX_CK_LV_SEL =0 and TX_CK_LV_PA[1:0]=11 See Figure 13. TX_CK_LV_SEL =1 and TX_CK_LV_PA[1:0]=11 See Figure 13. TX_CK_LV_SEL =0 and TX_CK_LV_PA[1:0]=11 TX_CK_LV_SEL is no connect or high TX_CK_LV_SEL is connected to low tCKH/tCKP See Figure 13. See Figure 12. See Figure 12. See Figure 15. See Figure 15. -- -- -- -- -- 45 -- -- 260 120 120 -- -- 622.08 -- -- -- -- 250 250 150 150 -- 55 300 300 -- ps ps ps ps MHz % ps ps ps Parameter Test Conditions Min. Typ. Max. Units
tSU
LVDS input data setup to LVDS input clock
320
--
--
ps
260
--
--
ps
tHD
LVDS input data hold from LVDS input clock
150 -- -- 45
-- 622.08 311.04 --
-- -- -- 55
ps MHz MHz %
fCLK
LVDS input clock frequency at OC-192 rate (TX_CK_LV_P/N) LVDS input clock frequency duty cycle (TX_CK_LV_P/N) LVDS transmitter common mode range RX_D_LV_P/N[15:0], RX_CK_LV_P/N, TX_CK622_P/N)
tDCCLK
DC Characteristics VOCM 100 load on line-to-line See Figure 11. See Figure 11. 100 load on line-to-line, SC_LV_ISET[1:0]=11 See Figure 11. 100 load on line-to-line, SC_LV_ISET[1:0]=10 See Figure 11. 100 load on line-to-line, SC_LV_ISET[1:0]=01 See Figure 11. 100 load on line-to-line, SC_LV_ISET[1:0]=00 0.95 -- 1.3 V mV (pk-pk) mV (pk-pk) mV (pk-pk) mV (pk-pk)
100
--
165
50
--
100
VOS
LVDS single-ended output voltage swing (RX_D_LV_P/N[15:0], RX_CK_LV_P/N)
80
--
125
130
--
210
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Lattice Semiconductor
XPIO 110GXS Data Sheet
Electrical Characteristics (Continued)
Low Speed Input/Output Specifications (Continued)
Over Recommended Operating Conditions
Symbol VICM VIH VIS Parameter LVDS receiver common mode range (TX_D_LV_P/N[15:0], TX_CK_LV_P/N) LVDS input voltage HIGH (TX_D_LV_P/N[15:0], TX_CK_LV_P/N) LVDS single-ended input voltage swing (TX_D_LV_P/N[15:0], TX_CK_LV_P/N) See Figure 11. Test Conditions See Figure 11. Min. 0.9 -- 100 Typ. -- -- -- Max. 1.6 2.4 600 Units V V mV (pk-pk)
LVCMOS Input/Output Specifications
Over Recommended Operating Conditions
Symbol VIH VIL IIH IIL VOH VOL IPU Parameter LVCMOS input high voltage LVCMOS input low voltage LVCMOS input high current LVCMOS input low current LVCMOS output high voltage LVCMOS output low voltage LVCMOS input pull-up current With 4mA load With 4mA load Test Conditions Min. 1.6 0 -- -- 2.0 0 90 Typ. -- -- -- -- -- -- -- Max. 2.6 0.8 10 10 2.5 0.4 170 Units V V A A V V A
Power Supply Specifications
Over Recommended Operating Conditions
Symbol PD IDD131 IDD252 Parameter Power dissipation 1.3V supply current 2.5V supply current Test Conditions Min. -- -- -- Typ. 0.8 390 130 Max. 1.05 460 160 Units W mA mA
1. 1.3V power supplies, including VDDAR, VDDAT, VDDL, VDDT, VDDR. 2. 2.5V power supplies, including VDDAR25, VDDAT25, VDDH.
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Lattice Semiconductor
XPIO 110GXS Data Sheet
Common Pin Assignments and Descriptions4
Pad Name Pin Description RX analog circuit ground TX analog circuit ground I/O ground GND
1, 3
Flip-chip BGA Ball Number4 E16, K14, L14, M15 F3, L5 D8, D9, E8, F7, F8, G8, H7, H8, H9, H10, J8, J9, J10, K8, K9, K10, L9, L10, M10, N10, P10, R10, R11, R12 C1, D12, D13, J12, M12, M16, N7, N14, P14, P15, R1 C12 F14, G13, H13, J14 F4, G5, H5, J4, K4, L4 E11, F10, J15, J16 M1, R8 C4, C5, C6, C7, C8, C9, C10, C11, D5, D10, D11, K11, L7, L8, L11, M6, M7, M8, M9, M11, N11, N12, P9, P11, P12 D4, E6, L12, R15, E10 F15, F16 J2, J3, M3 J11 F1 C2, C14, C15, C16, C17, D1, D14, D16, E1, E2, E4, E7, E13, E14, F5, F6, F12, F13, F17, G4, G6, G10, G11, H4, H6, H12, J7, J13, J17, K5, K6, K7, K12, K13, L6, L13, M2, M13, N2, N3, N5, N8, N9, N17, P3, P4, P7, P16, P17, R2, R14
Logic circuit ground PLL ground High-speed limit amplifier ground High-speed transmitter driver ground
VDDAR VDDAT VDDH VDDL VDDR VDDT VDDAR25 VDDAT25 NC2
RX analog circuit power TX analog circuit power I/O power Logic circuit power High-speed limit amplifier power High-speed transmitter driver power Reference circuit power Reference circuit power No connect
1. All grounds must be electrically connected at the board level. 2. NC pins should not be connected to any active signals, VDD or GND. 3. Balls for GND, VDDAR, VDDAT, VDDH, VDDL, VDDR, VDDT, VDDAR25 and VDDAT25 are connected within the substrate to their respective common signals. 4. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order ascending horizontally.
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Lattice Semiconductor
XPIO 110GXS Data Sheet
Output Pin Assignments and Descriptions
Pin Name TX_D_N TX_D_P TX_LOCK CK622OUT_N CK622OUT_P RX_CK_LV_P RX_CK_LV_N Pin Description 10 Gbps CML transmit data. See Figure 5. TX PLL lock indicator: TX LOCK = 1, internal TX_CLK locked to REF_CLK; TX LOCK = 0, PLL is unlocked. 622 MHz LVDS clock output. Phase is adjustable1 and locks to CMU or CDR clock.2 LVDS clock output. Clock is source synchronous to the LVDS receive, runs at 622MHz and is phase adjustable. Flip-chip Function BGA Ball # CML/ Out LVCMOS/ Out LVDS/ Out LVDS/ Out K3 L3 D7 R4 R5 U9 T9 T1, U1, T2, U2 T3, U3 T4, U4 T5, U5 T6, U6 T7, U7 T8, U8 T10, U10 T11, U11 T12, U12 T13, U13 T14, U14 T15, U15 T16, U16 T17, U17
RX_D_LV_N[15], RX_D_LV_P[15], RX_D_LV_N[14], RX_D_LV_P[14], RX_D_LV_N[13], RX_D_LV_P[13], RX_D_LV_N[12], RX_D_LV_P[12], RX_D_LV_N[11], RX_D_LV_P[11], RX_D_LV_N[10], RX_D_LV_P[10], RX_D_LV_N[9], RX_D_LV_P[9], RX_D_LV_N[8], RX_D_LV_P[8], LVDS data output. See Figure 8. RX_D_LV_N[7], RX_D_LV_P[7], RX_D_LV_N[6], RX_D_LV_P[6], RX_D_LV_N[5], RX_D_LV_P[5], RX_D_LV_N[4], RX_D_LV_P[4], RX_D_LV_N[3], RX_D_LV_P[3], RX_D_LV_N[2], RX_D_LV_P[2], RX_D_LV_N[1],RX_D_LV_P[1], RX_D_LV_N[0], RX_D_LV_P[0] Receiver PLL lock indicator. The PLL locks to REF_CK/RX_REF_CK. RX_LOCK = 1, receiver PLL frequency is within 300 ppm; RX_LOCK = 0, receiver PLL frequency is larger than 450 ppm; Frequency difference range is adjustable by SC_LOCK_DIFF[1:0]. 10 Gbps CML output, repeat data. This output repeats the data at the RX_D_P/N inputs when RX_D_RP_Enb = 0. This output can be used for diagnostic purposes and to evaluate the receivers limiting amplifier. These pins can be left unconnected if unused. FIFO error. 1 = error, 0 = normal operation.
LVDS/ Out
RX_LOCK
LVCMOS/ Out
M17
RX_D_RP_P3 RX_D_RP_N
CML/ Out LVCMOS/ Out
H14 G14
TX_FIFO_ERR
D6
1. CMU mode only. 2. Based on RX_REF_CK_Enb 3. Operation above 10.3Gbps is not supported.
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Lattice Semiconductor
XPIO 110GXS Data Sheet
Input and Analog Pin Assignments and Descriptions1
Pin Name RX_D_P, RX_D_N RX_REF_CK_P RX_REF_CK_N REF_CK_N2 REF_CK_P TX_CK_LV_N, TX_CK_LV_P 10 Gbps CML input. LVPECL/CML 155/622 MHz reference clock for RX. See Figure 7. Transmitter reference clock input, see Figure 7. REF_CK is the CMU reference clock. LVDS TX clock, 622 MHz/311 MHz selectable, phase adjustable. Pin Description Function CML/In CML/In or LVPECL/In CML/In CML/In LVDS/In LVDS/In Flip-chip BGA Ball # L15, K15 E17 D17 N1 P1 B9, A9 B17, A17 B16, A16 B15, A15 B14, A14 B13, A13 B12, A12 B11, A11 B10, A10 B8, A8 B7, A7 B6, A6 B5, A5 B4, A4 B3, A3 B2, A2 B1, A1 D15 E15 M4 N4 M14 P13 R13 R16 R17 G12
TX_D_LV_N[15], TX_D_LV_P[15] LVDS data input. See Figure 8. TX_D_LV_N[14], TX_D_LV_P[14] TX_D_LV_N[13], TX_D_LV_P[13] TX_D_LV_N[12], TX_D_LV_P[12] TX_D_LV_N[11], TX_D_LV_P[11] TX_D_LV_N[10], TX_D_LV_P[10] TX_D_LV_N[9], TX_D_LV_P[9] TX_D_LV_N[8], TX_D_LV_P[8] TX_D_LV_N[7], TX_D_LV_P[7] TX_D_LV_N[6], TX_D_LV_P[6] TX_D_LV_N[5], TX_D_LV_P[5] TX_D_LV_N[4], TX_D_LV_P[4] TX_D_LV_N[3], TX_D_LV_P[3] TX_D_LV_N[2], TX_D_LV_P[2] TX_D_LV_N[1], TX_D_LV_P[1] TX_D_LV_N[0], TX_D_LV_P[0] RX_FILT_EXTP RX_FILT_EXTN TX_FILT_EXTP TX_FILT_EXTN RX_REF_CK_Enb RX_LV_CKDLY[0] RX_LV_CKDLY[1] SC_LV_ISET[0] SC_LV_ISET[1] RX_LOS RX External Filter. See Figure 9. TX External Filter. See Figure 9. RX reference clock enable. LVDS output clock delay programming. LVDS output current settings. RX loss of signal. When RX_LOS is asserted, LVDS clock RX_CK_LV_P/N is driven out, and the LVDS data pins are muted (i.e. at differential 0). RX lose signal polarity change. Receive data repeater enable. RX PLL lock to reference. The RX PLL locks to the recovered data clock when this pin is unconnected/pulled high. The RX PLL locks to either RX_REF_CK or REF_CK depending on the state of RX_REF_CK_ENb. Lock indicate frequency resolution settings. Transmitter reset. Loopback enabled at parallel 622 MHz port. Loopback of TX 16b LVDS to RX 16b LVDS. FIFO initialization. SERDES LSB 1 first out selection. CML output current settings.
Analog Analog LVCMOS/In LVCMOS/In LVCMOS/In LVCMOS/In
RX_LOS_POL RX_D_RP_Enb RX_LOCK2REFb
LVCMOS/In LVCMOS/In LVCMOS/In
R7 H11 F11
SC_LOCK_DIFF[1] SC_LOCK_DIFF[0] RESET_TXb LB_P622_Enb LB_LVDS_Enb TX_FIFO_INIT SC_LSB1STb TX_CML_ISET[1] TX_CML_ISET[0]
LVCMOS/In LVCMOS/In LVCMOS/In LVCMOS/In LVCMOS/In LVCMOS/In LVCMOS/In
N13 N15 F9 E12 C13 D3 F2 J5 J1
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Lattice Semiconductor
XPIO 110GXS Data Sheet
Input and Analog Pin Assignments and Descriptions1 (Continued)
Pin Name TX_CK_LV_PA[0] TX_CK_LV_PA[1] TX_D_EN TX_CK622_PA[1] TX_CK622_PA[0] PWDN_TXb PWDN_RXb RESET_RXb CK622OUT_SEL REF_CK_SEL RX_LV_EN TX_CP_ISET[1] TX_CP_ISET[0] TX_LV_PLLBPb TX_CK_LV_SEL BIST ENb BIST LB SC[1] TX_CP_ISE[0] Pin Description LVDS TX clock adjustment for 622 MHz or 311 MHz mode. 10 Gbps CML TX enable. CLK622 timing adjustment. TX power down. RX power down. RX reset. CK622 enable. Ref CLK frequency selection. LVDS output enable. TX charge pump current setting. LVDS PLL bypass. Inverting phase of 622M clock TX_CK_LV_P/N is used to sample the input parallel data. Sets TX_CK_LV_P/N frequency. Enable built-in self test. Used for LVDS loopback. Configures LVDS loopback Function LVCMOS/In LVCMOS/In LVCMOS/In LVCMOS/In LVCMOS/In LVCMOS/In LVCMOS/In LVCMOS/In LVCMOS/In LVCMOS/In LVCMOS/In LVCMOS/In LVCMOS/In Flip-chip BGA Ball # G7 C3 J6 P2 N6 P5 N16 R6 P6 P8 R9 R3, M5 E9 G9 E5 D2, E3
1. All LVCMOS/In pins have built-in pullup resistors. 2. REF_CK is the CDR reference clock when RX_REF_CK_Enb = 1.
22
Lattice Semiconductor
XPIO 110GXS Data Sheet
Part Number Description
LS110GXS - X XXXXX X XX
Device Family LS = Lattice SERDES Device Number 110G = 1 Channel, 10Gbps Standard Support XS = XSBI (for 10G Ethernet) and SFI-4.1 (for OC-192) Optional Suffix ES = Engineering Samples Blank = Production Grade C = Commercial I = Industrial Package CF269 = 269 Flip-chip BGA Performance Grade 1 = 9.95 Gbps 2 = 9.95 - 10.31 Gbps
Ordering Information
Commercial
Part Number LS110GXS-1CF269C LS110GXS-2CF269C Supported Data Rates (Gbps) 9.953 9.953 to 10.31 Voltage 1.3V 1.3V Speed Grade -1 -2 Package fcBGA fcBGA Balls 269 269
Industrial
Part Number LS110GXS-1CF269I Supported Data Rates (Gbps) 9.953 Voltage 1.3V Speed Grade -1 Package fcBGA Balls 269
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